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Unable to sync endpoint clocks error CHR 0371

This document (7012577) is provided subject to the disclaimer at the end of this document.


Vivinet Assessor 3.x


When using later versions of Intel processors you will see this error occuring. This occurs because the Intel Speed Step feature has been enabled in the BIOS. This causes the high percision timer on the CPU to drift. This drift in time keeping mechanism will cause the two endpoints to not properly syncronize.


Access the BIOS on the machine and disable the Intel Speed Step processor performance feature. Please consult the manufactures instructions for how to access the BIOS on the machine, as this will vary.


The two endpoints are unable to agree upon a time as the high percision timer will drift when Intel Speed Step is enabled.


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  • Document ID:7012577
  • Creation Date:07-JUN-13
  • Modified Date:07-JUN-13
    • NetIQVivinet Assessor

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